1. Field of the Invention
The present invention relates to microprocessor instructions, and more particularly, to a system and method of using common adder circuitry to perform at least two instructions including a horizontal minimum instruction and a sum of absolute differences instruction.
2. Description of the Related Art
Modern day microprocessors are often configured to perform media instructions to improve the efficiency of multimedia applications and the like. For example, one or more media instructions may be included in the microprocessor architecture to identify a horizontal minimum, which is the minimum one of a set of digital values and its corresponding location in a bus or register or the like. A specific example is the PHMINPOSUW instruction described in the SSE4 Programming Reference manual by Intel®, which uses an array of 16-bit magnitude comparators or the like in a conventional configuration. Another example is the MPSADBW instruction which sums the absolute differences between a first set of digital values and sequential groups of a second set of digital values. In a conventional configuration, the MPSADBW instruction uses an array of 8-bit adders or the like to compare the digital values and provide the sums of absolute differences values. A conventional microprocessor configured to perform both of these instructions incorporates both the array of magnitude comparators and the adders which consumes a significant amount of space on the microprocessor die.